The present invention relates to a heterojunction bipolar transistor and an integrated circuit device such as a photoreceiver opto-electro integrated circuit comprising the heterojunction bipolar transistors and a pin photodiode.
In the heterojunction bipolar transistor, the emitter has a wider band gap than that of a base layer, so emitter injection efficiency can be advantageously kept high even when the impurity concentration of the base layer is high. In addition, the heterojunction bipolar transistor can be operated at a speed higher than that of a homojunction bipolar transistor because of the excellent electron transport properties of the compound semiconductor used in the base and/or collector layers. One of the typical examples of this type of transistors is an npn-InP/InGaAs-based heterojunction bipolar transistor.
FIGS. 3A and 3B respectively show the energy band diagram and layer structure of a conventional InP/InGaAs heterojunction bipolar transistor.
This heterojunction bipolar transistor is constituted by an InGaAs collector contact layer 52 containing a high-concentration n-type impurity formed on a semi-insulating InP substrate, an InGaAs collector layer 57 containing a low-concentration n-type impurity, an InGaAs base layer 58 containing a high-concentration p-type impurity, an InP emitter layer 59 containing an n-type impurity, and an InGaAs emitter contact layer 60 containing a high-concentration n-type impurity.
A collector electrode, a base electrode, and an emitter electrode are formed on the collector contact layer 52, the base layer 58, and the emitter contact layer 60, respectively, and each of these electrodes consists of Ti/Pt/Au.
Since this structure uses InP as the emitter layer 59, which has a band gap wider than that of the base layer 58, emitter injection efficiency can be kept high even at a high doping concentration of the base layer. In addition, due to the excellent electron transport properties of, InGaAs, the transistor can operate at a high-speed speed.
In a heterojunction bipolar transistor, it is important to decrease transit time of electrons in the collector to increase the operation speed. As one of structures for realizing this, a collector structure of ballistic collection transistor (to be referred to as a BCT hereinafter) has been proposed (T. Ishibashi and Y. Yamauchi, "A possible near-ballistic collection in AlGaAs/GaAs HBT with a modified collector structure, "IEEE Trans. Electron Devices, vol. 35, pp. 401-404, 1988).
As shown in FIGS. 5A and 5B, a collector layer 57 of the InP/InGaAs BCT structure is constituted by an undoped InGaAs layer 57b, an InGaAs layer 57c containing a p-type impurity at a high concentration, and an InGaAs layer 57d containing an n-type impurity at a high concentration. The same reference numerals as in FIG. 3B denote the same parts in FIG. 5B.
The InGaAs layer 57c and the InGaAs layer 57d constitute a p-n junction to form a potential cliff near the interface between the collector and the collector contact layer.
This potential cliff reduces the potential change in the collector layer 57b, and suppresses the transition of electrons passing through the collector layer 57b from T-valley to L-valley. As a result, the transit time of electrons in a collector is shortened to decrease the operation time of the transistor.
However, the heterojunction bipolar transistors shown in FIGS. 3A, 3B, 5A, and 5B have a low collector breakdown voltage because a strong electric field is applied to a semiconductor with a low band gap energy located near the interface between the collector and the collector contact layer.
The situation is very severe especially in the heterojunction bipolar transistor using InGaAs as the material of the collector, which has a band gap energy of the InGaAs is as low as 0.76 eV.
When the emitter is grounded, and collector current density is increased, the collector breakdown voltage becomes very low due to the high ionization coefficient.
In addition, in the BCT structure, a steeper potential change is produced near the interface between the collector layer and the collector contact layer to make the problem of the breakdown voltage more serious in a transistor using an InP/InGaAs-based material.
FIG. 4 shows a structure of a photoreceiver opto-electro integrated circuit is constituted by conventional heterojunction bipolar transistors and a Pin photodiode which uses the same layers as the base layer 58, the collector layer 57, and the collector contact layer 52 of the above heterojunction bipolar transistor. This structure is described in, for example, K. D. Pedrotti, N. H. Sheng, R. L. Pierson, Jr., C. W. Farley, M. J. Rosker and M. F. Chang, "Monolithic ultrahigh-speed GaAs HBT optical integrated receivers", Tsch. Dig. 1991 GaAs IC symp., pp. 205-208.
The same reference numerals as in FIGS. 3A and 3B denote the same parts in FIG. 4. In FIG. 4, reference numeral 51 denotes a semi-insulating InP substrate; 52a, an InGaAs layer containing n-type impurities at a high concentration; 57a, an intermediate InGaAs layer; and 58a, p-type layer consisting of InGaAs containing p-type impurities at a high concentration. The n-type layer 52a, the intermediate layer 57a, and the p-type layer 58a constitute a Pin photodiode.
Referring to FIG. 4, reference numeral 61 denotes an emitter electrode formed on the emitter contact layer 60; 62, a base electrode formed on the base layer 58; 63, a collector electrode formed on the collector contact layer 52; 62a, an ohmic electrode formed on the p-type layer 58a; and 63a, an ohmic electrode formed on the n-type layer 52a. In this case, the collector contact layer 52 and the n-type layer 52a, the collector layer 57 and the intermediate layer 57a, and the p-type base layer 58 and the p-type layer 58a are, respectively, simultaneously formed by epitaxial growth. In addition, the base electrode 62 and the ohmic electrode 62a, and the collector electrode 63 and the ohmic electrode 63a, respectively, are simultaneously formed.
In this manner, the heterojunction bipolar transistor and the photodiode are formed on the same substrate.
The photoreceiver opto-electro integrated circuit with the above Arrangement has not only a serious problem of the low collector breakdown voltage as described above, but also the following problem.
In an integrated circuit implemented with a pin photodiode which is formed on the same semiconductor substrate using the base layer, collector layer, and collector contact layer of the heterojunction bipolar transistor, the response speed of an photo-excitation current of a photodiode with respect to incident light is not easily increased due to the following reason. That is, the incident light reaches the n-type layer deeper than the intermediate layer to generate electron-hole carrier pairs in the n-type layer, and the holes contribute to the photo-excitation current of the photodiode.
The response of the photodiode is delayed because of the transit time of the holes generated in the deep portion of the collector contact layer (n-type layer) to the base layer by diffusion or drifting.
In this state, even if a photoreceiver opto-electro integrated circuit is realized by forming a photodiode on the substrate on which the electronic circuit is formed, and an electronic circuit operates at a high speed, the response speed of the photodiode is low. For this reason, the operation speed of the integrated circuit cannot be easily increased.